AISB convention 2017

  In the run up to AISB2017 convention, I've asked Joanna Bryson, from the organising team, to answer few questions about the convention and what comes with it. Mohammad Majid al-Rifaie (https://twitter.com/mohmaj) Tu...


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Harold Cohen

Harold Cohen, tireless computer art pioneer dies at 87   Harold Cohen at the Tate (1983) Aaron image in background   Harold Cohen died at 87 in his studio on 27th April 2016 in Encintias California, USA.The first time I hear...


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Dancing with Pixies?...

At TEDx Tottenham, London Mark Bishop (the former chair of the Society) demonstrates that if the ongoing EU flagship science project - the 1.6 billion dollar "Human Brain Project” - ultimately succeeds in understanding all as...


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Computerised Minds. ...

A video sponsored by the society discusses Searle's Chinese Room Argument (CRA) and the heated debates surrounding it. In this video, which is accessible to the general public and those with interest in AI, Olly's Philosophy Tube ...


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Connection Science

All individual members of The Society for the Study of Artificial Intelligence and Simulation of Behaviour have a personal subscription to the Taylor Francis journal Connection Science as part of their membership. How to Acce...


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Notice

AISB event Bulletin Item

CALL FOR PARTICIPATION: What Architecture for Neural Hardware?, 26th October, LONDON


Title: What Architecture for Neural Hardware? Speaker: Alex Rast, School of Computer Science, University of Manchester Wednesday 26th October - 16:00-17:30 - Room 343, Huxley Building, South Kensington campus, Imperial College, London, SW7 2A, UK

Abstract: Dedicated hardware is becoming increasingly essential to simulate emerging very large 
scale neural models. However, the question of what the appropriate architecture is for such neural 
hardware must take into account the fact that different research groups who might wish to use the 
hardware may have very different objectives. Previous generations of "neuroprocessor" and 
"neuromorphic" chips, tended either to hardwire a specific model into the chip, or offer no real 
advantage over conventional digital processing, meaning as a consequence their interest rarely 
extended beyond a narrow target audience (usually collaborators of the chip designers). A new 
approach: the "neuromimetic" architecture, maintains the neural optimisation of dedicated chips 
while offering FPGA-like universal configurability. As a leading example of this emerging 
architecture, SpiNNaker is a parallel multiprocessor employing an asynchronous event-driven model 
with configurable dedicated hardware on the chip to support real-time neural simulation. This makes
it capable of supporting multiple models of the neural dynamics, possibly operating simultaneously 
within the same system. Implementing these models on-chip uses an integrated library-based tool 
chain that allows a modeller to input a high-level description and use an automated process to 
generate an on-chip simulation. Results from simulation demonstrate SpiNNaker's ability to support 
multiple heterogeneous neural models at reasonable scale. SpiNNaker's asynchronous virtual 
architecture permits greater scope for model exploration, with scalable levels of functional and 
temporal abstraction, than conventional (or neuromorphic) computing platforms. The neuromimetic 
architecture opens an intriguing possibility that makes it a compelling choice: using the hardware
to establish useful abstractions of biological neural dynamics that could lead to a functional 
model of neural computation.

Biography: Alex Rast is a Research Associate with the SpiNNaker Group at the University of 
Manchester. He received his Ph.D. from the University of Manchester in 2010 for work on model 
libraries for configurable neural systems. Prior to joining the University of Manchester he worked 
at Inficom, Inc., a startup company doing research into advanced processing and communications 
technologies. His current research interests include extending and standardising neural model 
libraries including classical models such as the MLP, tool development for neural hardware, 
parallel and alternative hardware architectures, and programming tools for parallel systems.